1. Field of the Invention
This invention relates to a display device used as a display unit of electronic devices and to a substrate for the display device.
2. Description of the Related Art
[First Prior Art]
FIG. 13 illustrates a pixel on a TFT substrate 102 for a conventional liquid crystal display device of the active matrix type. On the TFT substrate 102 are formed a plurality of gate bus lines 112 extending in the right-and-left direction in the drawing. On the TFT substrate 102 are further formed a plurality of drain bus lines 116 extending up and down in the drawing intersecting the plurality of gate bus lines 112 via an insulating film that is not shown. Regions defined by the gate bus lines 112 and the drain bus lines 116 serve as pixel regions. On the TFT substrate 102 are formed storage capacitor bus lines 120 traversing nearly the centers of the respective pixel regions and extending in parallel with the gate bus lines 112.
TFTs 117 are formed in the vicinity of the positions where the gate bus lines 112 intersect the drain bus lines 116. Drain electrodes 118 of the TFTs 117 are drawn from the drain bus lines 116, and are so formed that the end portions thereof are positioned on one end side on a channel protection film 119 formed on an operation semiconductor layer (not shown) on the gate bus lines 112. Source electrodes 124 of the TFTs 117 are so formed as to be positioned on the other end side on the channel protection film 119. In this constitution, the gate bus lines 112 just under the channel protection film 119 work as gate electrodes of the TFTs 117.
A pixel electrode 122 is formed on the pixel regions defined by the gate bus lines 112 and drain bus lines 116. The pixel electrode 122 is electrically connected to the source electrode 124 of the TFT 117 through a contact hole 126.
FIG. 14 illustrates, in cross section, the TFT substrate 102 cut along the line A-A in FIG. 13. An insulating film (gate-insulating film) 114 is formed on a glass substrate 110. The drain bus lines 116 are formed on the insulating film 114. A protection film 128 is formed on the whole surface of the substrate on the drain bus lines 116. Pixel electrodes 122 are formed on the protection film 128.
The liquid crystal display device has the TFT substrate 102, an opposite substrate arranged facing the TFT substrate 102, and liquid crystals sealed between the two substrates. A predetermined half-tone voltage is applied to the drain bus lines 116. When the TFT 117 is turned on, the half-tone voltage is applied from the drain electrode 118 to the pixel electrode 122 through the source electrode 124. The intensity of an electric field acting on the liquid crystals of the pixels varies depending upon a potential difference between a common voltage applied to a common electrode formed on the opposite substrate and the half-tone voltage applied to the pixel electrode 122. The direction of inclination of the liquid crystal molecules changes depending upon a change in the intensity of the electric field, whereby the light transmission factor varies and a desired half-tone display is realized.
FIG. 15 illustrates an equivalent circuit of a conventional liquid crystal display device. The constitution of the liquid crystal display device will be described by using FIG. 15 while making reference to FIGS. 13 and 14. Referring to FIG. 15, a liquid crystal capacitance Clc and a storage capacitor Cs are formed in each pixel. The liquid crystal capacitance Clc is of a structure in which a dielectric liquid crystal layer is sandwiched by the pixel electrode 122 and the common electrode on the opposite substrate 104. A common voltage Vcom is applied to the common electrode. The storage capacitor Cs is connected in parallel with the liquid crystal capacitance Clc. The storage capacitor Cs is of a structure in which a dielectric protection film 128 is sandwiched by the storage capacitor bus line 120 and the pixel electrode 122. To increase the capacitance, an intermediate electrode is often provided between the storage capacitor bus line 120 and the pixel electrode 122. The storage capacitor Cs is used for holding the electric charge stored in the pixel electrode 122 while the TFT 117 is being turned off within a display frame period. The plurality of storage capacitor bus lines 120 arranged on the TFT substrate 102 in parallel with the gate bus lines 112, are respectively, electrically connected to a common storage capacitor wiring 130 arranged nearly in parallel with the drain bus lines 116 outside the display region. A predetermined voltage is applied to the storage capacitor bus lines 120 via the common storage capacitor wiring 130. Here, for example, the common voltage Vcom applied to the common electrode of the opposite substrate 104, is applied to the storage capacitor bus lines 120.
FIG. 16 illustrates a drive waveform of when a pixel on the TFT substrate 102 is driven, and wherein the abscissa represents the time and the ordinate represents the voltage level. In FIG. 16, when a predetermined gate pulse voltage Vg is input to the gate electrode of TFT 117 in the pixel causing the TFT 117 to be turned on, the half-tone voltage Vd on the drain bus line 116 to which the drain electrode 118 of the TFT 117 is connected, is written onto the pixel electrode 122 of the pixel.
To prevent the liquid crystals from deteriorating, in general, the half-tone voltage is applied to the liquid crystals relying on a frame inversion drive of which the polarity is inverted with the common voltage Vcom as a center every time when the half-tone voltage is rewritten (i.e., for every display frame). FIG. 16 illustrates a so-called line inversion drive in which the polarity of the half-tone voltage is inverted for every neighboring gate bus line in addition to inverting the frame.
In this frame inversion drive, a voltage obtained by inverting the polarity of the half-tone voltage written in the preceding frame, is written onto the pixel electrode 122 in the next frame. When the half-tone voltage has a large amplitude, therefore, the voltage at the pixel electrode 122 undergoes a great change at the time of writing the half-tone voltage.
When the voltage greatly changes on the pixel electrode 122, the voltage Vc on the side of the storage capacitor bus line 120 constituting the storage capacitor Cs often deviates from the common voltage Vcom. A change in the voltage Vc on the side of the storage capacitor bus line 120 attenuates with a predetermined time constant based on the resistance component and capacitance component in the wiring inclusive of the common storage capacitor wiring 130, and the voltage Vc on the side of the storage capacitor bus line 120 approaches again the common voltage Vcom. When the resistance component and the capacitance component are great, however, the voltage Vc of the storage capacitor bus line 120 becomes no longer capable of returning back to the common voltage Vcom within a period in which TFT 117 is turned on. Should that happen, the desired half-tone voltage Vd is not written but, instead, a potential difference Vp (<Vd) between the half-tone voltage Vd and the voltage Vc on the side of the storage capacitor bus line 120 is written into the pixel electrode 122, deteriorating the quality of display of the liquid crystal display device.
To solve this problem, there has been proposed a method that the common storage capacitor wiring 130 is formed by two layers, i.e., a metal layer forming the gate bus line 112 and a metal layer forming the drain bus line 116, in an attempt to increase the sum of sectional areas of the common storage capacitor wiring 130 and to decrease the resistance component of the common storage capacitor wiring 130.
In order to electrically connect the common storage capacitor wiring 130 formed by the metal layer of the gate bus line 112 to the common storage capacitor wiring 130 formed by the metal layer of the drain bus line 116, however, it is necessary to form a contact hole by perforating the insulating film on the common storage capacitor wiring 130 formed by using the metal layer of the gate bus line 112 and to electrically connect the two common storage capacitor wirings 130 through the contact hole. This makes complex the step of producing the liquid crystal display device, and there is a problem that the cost of production cannot be decreased.
[Second Prior Art]
The liquid crystal display device of the active matrix type is formed by sealing liquid crystals between the opposite substrate on which the common electrode (opposite electrode) is formed over the whole surface thereof and the TFT substrate having pixel electrodes formed for the plurality of respective pixel regions and thin-film transistors (TFTs) connected as switching elements to the respective pixel electrodes. As required, the liquid crystal display device is imparted with a polarizing function by using color filters formed on the opposite substrate.
When the TFT on the TFT substrate is turned on, a predetermined potential is written for each pixel electrode, and the voltage applied to the liquid crystal layer is controlled for each pixel region. The voltage applied to the liquid crystal layer must be maintained until the next frame even when the TFT is turned off. However, the potential of the pixel electrode varies within a frame period due to parasitic capacitance formed in the TFT and leakage current between the pixel electrode and the common electrode. Therefore, each pixel region is provided with a storage capacitor Cs which is connected in parallel with the pixel capacitance Clc and which uses the pixel electrode as one electrode. The storage capacitor suppresses the variation in the potential of the pixel electrode, and the voltage applied to the liquid crystal layer is maintained for one frame period.
The liquid crystal display devices can be grouped into those of the Cs-on-gate type in which the gate electrodes of the neighboring pixels are used as the other electrodes of the storage capacitors and the capacitance is formed during the off state when no voltage is being applied to the gate electrodes, and those of the independent Cs type in which the storage capacitor bus lines that are independently formed are used as the other electrodes. The liquid crystal display device of the Cs-on-gate type requires no storage capacitor bus line, and features a higher aperture ratio of pixels than that of the liquid crystal display device of the independent Cs type.
Japanese Laid-Open Patent Publication No. 202153/1994 discloses a technology as described below in an attempt to simplify the process for manufacturing the liquid crystal display device and the steps of production. On the TFT substrate of the liquid crystal display device, there are formed gate electrodes of TFTs, gate bus lines and storage capacitor bus lines by using a first electrically conducting material. An insulating film is formed on the gate electrodes, gate bus lines and storage capacitor bus lines. On the insulating film, there are formed source/drain electrodes of TFTs and drain bus lines by using a second electrically conducting material. On the insulating film are further formed storage capacitor electrodes (intermediate electrodes) for forming storage capacitors relative to the storage capacitor bus lines by using the second electrically conducting material. A protection film is formed on the source/drain electrodes, drain bus lines and storage capacitor electrodes. Contact holes are formed by perforating the protection film on the source electrodes, storage capacitor electrodes and drain bus line terminals at the ends of the drain bus lines. Further, contact holes are formed by perforating the protection film and the insulating film on the gate bus line terminals at the ends of the gate bus lines and on the storage capacitor bus line terminals (hereinafter also simply referred to as external connection terminals) at the ends of the storage capacitor bus lines simultaneously with the formation of the above contact holes by using the same photomask. Then, a pixel electrode made of a third electrically conducting material is formed for each of the pixels. The pixel electrode is electrically connected to the source electrode and to the storage capacitor electrode through the contact holes.
In the liquid crystal display device of the independent Cs type, there is formed a common storage capacitor wiring for electrically connecting the plurality of storage capacitor bus lines to maintain the storage capacitor bus lines at the same potential. A predetermined voltage is applied to the common storage capacitor wiring through an external connection terminal. Japanese Laid-Open Patent Publication 265688/1987 discloses a common storage capacitor wiring by bundling the storage capacitor bus lines. Japanese Laid-Open Patent Publication 72321/1991 discloses the constitution of a common storage capacitor wiring for forming an additional capacitance relative to the gate bus line outside the display region. Japanese Laid-Open Patent Publication 160076/1997 discloses the constitution for electrically connecting the storage capacitor bus lines to the common storage capacitor wiring through the contact holes formed on the storage capacitor bus lines and on the common storage capacitor wiring, and through connection wirings formed between the two contact holes. Japanese Laid-Open Patent Publication 218930/1995 discloses the constitution provided with TFTs of the normal stagger type and in which the storage capacitor bus lines are formed by using the same material as the one forming the light shield film instead of using the same material as the one forming the gate electrodes.
In the liquid crystal display device of the independent Cs type, the common electrode is electrically connected to the storage capacitor bus lines through transfer portions formed outside the display region to equalize the potential between the common electrode formed on the opposite substrate and the storage capacitor bus lines. Japanese Laid-Open Patent Publication 234220/1996 discloses an example of arranging a plurality of transfer portions along the outer circumference of the substrate. Japanese Laid-Open Patent Publication 136949/1996 discloses the constitution equipped with TFTs of the normal stagger type and forming the connection terminals of the transfer portions by using the same material as the one forming the light shield film instead of using the same material as the one forming the gate electrode. Japanese Laid-Open Patent Publication 15646/1997 discloses the constitution of connecting the common storage capacitor wiring to the common electrode through an additional resistor.
FIG. 17 illustrates the constitution of a conventional substrate for display devices. On the display region of the TFT substrate 102 surrounded by a broken line as shown in FIG. 17, there are formed a plurality of gate bus lines 112 (four lines in FIG. 17) in parallel with each other and extending in the right-and-left direction in the drawing. Gate bus line terminals 156 are formed at the ends of the respective gate bus lines 112 on the left in the drawing.
On the display region of the TFT substrate 102, further, there are formed a plurality of storage capacitor bus lines 120 (four lines in FIG. 17) in parallel with the gate bus lines 112 by using the same material as the one forming the gate bus lines 112. At the ends of the storage capacitor bus lines 120 on the right in the drawing, there is formed a common storage capacitor wiring 160 by using the same material as the one forming the gate bus lines 112 and the storage capacitor bus lines 120, and extending in the up-and-down direction in the drawing. The common storage capacitor wiring 160 is connected to the plurality of storage capacitor bus lines 120. Though not illustrated, on the display region are formed a plurality of drain bus lines in parallel with each other and extending in the up-and-down direction in the drawing, intersecting the gate bus lines 112 and the storage capacitor bus lines 120 via an insulating film.
External connection terminals 142 are formed on the TFT substrate 102 at left upper, right upper and right lower three ends in the drawing. The external connection terminals 142 are connected to the storage capacitor bus lines 120 or to the common storage capacitor wiring 160. A predetermined voltage is applied from an external side to the storage capacitor bus lines 120 through the external connection terminals 142.
In the vicinity of the common storage capacitor wiring 160, there are arranged transfer-forming regions 144 that will be connected to the common electrode on the opposite substrate through the transfer portions when the substrate is stuck to the opposite substrate (not shown). On the transfer-forming regions 144 are formed connection pads for example, by using the same material as the one forming the gate bus lines 112. The connection pads are electrically connected to the common storage capacitor wiring 160. In the constitution shown in FIG. 17, however, a problem arouses in regard to a delay of the signals at the ends of the storage capacitor bus lines 120 which are not connected to the external connection terminals 142.
FIG. 18 illustrates the constitution of another conventional substrate for display devices. On the TFT substrate 102 as shown in FIG. 18, there are formed a plurality of gate bus lines 112 (four lines in FIG. 18) in parallel with each other and extending in the right-and-left direction in the drawing. Gate bus line terminals 156 are respectively formed at both ends of the gate bus lines 112.
On the TFT substrate 102, further, there are formed a plurality of storage capacitor bus lines 120 (four lines in FIG. 18) in parallel with the gate bus lines 112 by using the same material as the one forming the gate bus line 112. At the ends of the storage capacitor bus lines 120 on the right in the drawing, there is formed a common storage capacitor wiring 160 by using an electrically conducting material different from the material forming the gate bus lines 120, and extending in the up-and-down direction in the drawing. The common storage capacitor wiring 160 is connected to the plurality of storage capacitor bus lines 120. At the ends of the storage capacitor bus line 120 on the left in the drawing, there is formed a common storage capacitor wiring 161 by using an electrically conducting material different from the material forming the storage capacitor bus lines 120 and extending in the up-and-down direction in the drawing. The common storage capacitor wiring 161 is connected to a plurality of storage capacitor bus lines 120.
In this constitution, the common storage capacitor wirings 160 and 161 are formed on both sides of the storage capacitor bus lines 120 and are applied with a predetermined voltage through the external connection terminals. As compared to the constitution illustrated in FIG. 17, the additional capacitance C and the electric resistance R can be nearly halved, suppressing a delay of signals through the storage capacitor bus lines 120. According to this constitution, however, it is necessary to newly form the common storage capacitor wirings 160 and 161 of an electrically conducting material different from the material forming the storage capacitor bus lines 120, arousing a problem of an increase in the number of production steps.
In recent years, the length of the storage capacitor bus lines 120 is increasing and the area of the common electrode which is a surface electrode is increasing, accompanied by an increase in the size of the display screen of the liquid crystal display devices. This, however, is accompanied by a further increase in the electric resistance in the storage capacitor bus lines 120 and in the common electrode. To decrease the electric resistance of the storage capacitor bus lines 120, the width of the wiring must be increased or the thickness thereof (film thickness) must be increased. However, an increase in the width of the storage capacitor bus lines 120 results in a decrease in the numerical aperture. Besides, limitation is imposed on increasing the thickness of the storage capacitor bus lines 120 and an increased period of time is required for forming a film from which the storage capacitor bus lines are formed in the step of production.
Further, as the pixels of the liquid crystal display device become highly fine, the number of intersection regions increases for enabling the storage capacitor bus lines 120 to intersect the drain bus lines via an insulating film. This results in a further increase in the additional capacitance of the storage capacitor bus lines 120.
As the electric resistance and additional capacitance of the storage capacitor bus line 120 increase, there occurs a delay of the signals for the compensation of the pixel potential based on a CR time constant determined by the product of the electric resistance and the additional capacitance. A delay of the signals causes a decrease in the quality of display of the liquid crystal display device.
As the pixels become highly fine, furthermore, the number of the gate bus lines also increases. If the frame period does not change, therefore, the time for writing the pixel potential assigned to each gate bus line becomes short. Therefore, there is further a problem of delays of the signals.
In the liquid crystal display device of the Cs-on-gate type which forms the storage capacitor only when the gate electrode has not been driven, in particular, the CR time constant required for the gate bus lines becomes more strict than the CR time constant required for the storage capacitor bus lines and the gate bus lines of the liquid crystal display device of the independent Cs type. Therefore, a highly fine liquid crystal display device of a large screen is constructed in the independent Cs type. In the device of the independent Cs type, too, it is desired to further decrease the resistance to satisfy the resistance required in the vicinity of the signal input terminals of the bus lines and at the ends of the bus lines distant from the input terminals. As for the common electrode, too, it is desired to further decrease the resistance to satisfy the resistance required in the vicinity of the signal input terminals and at the ends distant from the input terminals.
When the resistance cannot be decreased to a sufficient degree, a voltage different from the desired voltage is applied across the pixel electrode and the common electrode. In the liquid crystal display device of the normally white mode, therefore, there arouses a problem in that display unevenness (brightness inclination) occurs causing the pixels connected to the ends of the bus lines to appear more white than a desired half-tone. In the liquid crystal display device of the normally black mode, similarly, there arouses a problem in that display unevenness occurs causing the pixels connected to the ends of the bus lines to appear more black than a desired half-tone. These problems related to the display unevenness cannot be solved relying simply upon the storage capacitor bus lines or the common electrode alone.